library verilog;
use verilog.vl_types.all;
entity i2c_master is
    generic(
        SYS_CLOCK       : integer := 20000000
    );
    port(
        clk             : in     vl_logic;
        reset           : in     vl_logic;
        i_req           : in     vl_logic;
        i_rw            : in     vl_logic;
        i_fast_mode     : in     vl_logic;
        i_dev_addr      : in     vl_logic_vector(6 downto 0);
        i_data          : in     vl_logic_vector(7 downto 0);
        o_data          : out    vl_logic_vector(7 downto 0);
        o_busy          : out    vl_logic;
        o_ack_error     : out    vl_logic;
        sda             : inout  vl_logic;
        scl             : inout  vl_logic
    );
    attribute mti_svvh_generic_type : integer;
    attribute mti_svvh_generic_type of SYS_CLOCK : constant is 1;
end i2c_master;
